A ubiquitous image sensor technology used in digital cameras is the charge-coupled device (CCD) imager. In a typical CCD imager, signal charge representative of incident radiation is accumulated in an array of pixels in an image area. Following an integration period, the signal charge is transferred to an output register by applying appropriate clocking or drive pulses to control electrodes. The signal charge is then read out from the output register and applied to a charge detection circuit to produce a voltage, which is representative of the amount of signal charge.
It has been found that, with the application of proper gate potentials, a form of gain via impact ionization can be achieved in a CCD device. In a thesis entitled “Avalanche Gain In Charge Coupled Devices,” submitted to the Massachusetts Institute of Technology in August of 1986, Stephanie A. Gagar (hereinafter “Gager”) suggested the incorporation of an avalanche multiplication of charge on a charge coupled device. Referring now to FIG. 1A, charge 2 is collected and accumulated under a gate 4 in a potential well 6. The accumulated charge 2 is then transferred through an intermediate gate 8 to a storage gate 10 where it is temporarily stored. The original gate 4 wherein the charge was first accumulated is then biased into avalanching. Referring now to FIG. 1B, charge is then transferred back from the temporary holding gate 10 to the accumulating gate 4 which is now biased as an avalanching gate. This is accomplished by pulsing the holding gate 10 to a lower potential and transferring the charge through the intermediate gate 8 to the avalanching region. For further gain, this procedure is repeated multiple times, i.e. 100 to 500 times, to build up charge. The gain per avalanche transfer is roughly 1.015×. The gain after N avalanche transfers is roughly (1.015)N, For N equal to 400, the resulting gain is about 386. Once sufficient charge has been built up, the charge is moved off of the CCD gates to a charge sensitive amplifier for amplification and read out.
A second design employing impact ionization can be found in U.S. Pat. No. 6,444,968 to Burt et al. (hereinafter “Burt et al.”). The Burt et al. CCD imaging architecture is depicted in FIG. 2. The Burt et al. CCD comprises an image area 12 containing a plurality of pixels, a store section 14 and an output or read-out register 16. The output register 16 is extended in a linear direction to a serial electron multiplication register 18, the output of which is connected to a charge detection circuit 20.
During operation of the device, incident radiation is converted at the image area 12 into signal charge. Following the image acquisition (integration) period, drive pulses are applied to control electrodes 22 to transfer the charge accumulated at the pixels of the image area 12 to the store section 14. Simultaneously with this, drive signals are also applied to control electrodes 24 at the store section 14 to cause charge to be transferred from row to row, the last row of charge being transferred in parallel to the output register 16.
When a row of signal charge has been transferred into the output register 16, appropriate drive pulses are applied to the electrodes 26 to sequentially transfer the charge from the elements of the output register to those of the electron multiplication register 18. To achieve multiplication of charge in each of the elements of the multiplication register 18, sufficiently high amplitude drive pulses are applied to control electrodes 28 to both transfer signal charge from one element to the next adjacent element and also to increase the level of signal charge by an amount determined by the amplitude of the drive pulses. Each signal charge packet stored in the output register 20 undergoes an identical multiplication process as each travels through all the elements of the multiplication register 18, thereby providing an overall high gain.
Unfortunately for the Burt et al. design, the increasing demand from the consumer market to supply higher and higher resolution CCD cameras has required designers to increase the number of pixels in the CCD image sensors that are used in these products. At the same time the competitive pressures to maintain or reduce the cost of these sensors necessitate the reduction of chip size and consequently the reduction of the active pixel area. The separate imaging area and storage area in the Burt et al. design goes against this trend, resulting in a large size imager that is costly.
Accordingly, what would be desirable, but has not yet been provided, is a solid state imager which provides the functionality of both CCD imaging arrays and amplification at a reduced overall footprint and cost.